// FPGA projects using Verilog/ VHDL // fpga4student.com: FPGA projects, Verilog projects, VHDL projects // Verilog code for up-down counter module updowncounter( input clk, reset,updown, output 3: 0 counter ); reg 3: 0 counterupdown; // down counter always @( posedge clk or posedge reset) begin if(reset) counterupdown. // FPGA projects using Verilog/ VHDL // fpga4student.com: FPGA projects, Verilog projects, VHDL projects // Verilog code for random counter with testbench // Testbench Verilog code for random counter module randomcountertestbench; reg clk, reset; reg 4: 0 initializedvalue; wire 4: 0 counterrandom; randomcounterlfsr dut( clk, reset, initializedvalue, counterrandom); initial begin clk = 0; forever # 5 clk =clk; end initial begin reset = 0; initializedvalue = 5'b11111; # 20; reset = 1; end endmodule.
My homework is to design a Serial Adder in Verilog using a shift register module, a full adder module, and a D Flip-Flop module. I know my full adder and flip flop modules are correct, but I am not so sure about my shift register. The shift register is 8 bits: Inputs for the shift register are: Si.